Efficient FPGA Implementation of Feedback Perceptron for Hardware Acceleration

Artificial Neural Networks (ANNs) have revolutionized machine learning, mimicking human cognitive abilities to recognize patterns and make decisions. The perceptron, a fundamental unit in ANNs, forms the basis for complex network structures. This paper introduces a novel approach to perceptrons by incorporating a feedback mechanism using a gain factor, replacing conventional learning rates. The proposed method aims to optimize network performance while adapting to hardware constraints. Implementation of MNIST and Heart Attack datasets showcase the superiority of the proposed approach over traditional methods, revealing substantial accuracy improvements across various activation functions (Sign, Step, and Sigmoid) in both single perceptron and multilayer perceptron (MLP) architectures. The proposed method achieves significant accuracy of 96.80% with the MNIST dataset, and 88.52% with the Heart Attack dataset compared to other methods. It has a small overhead in power consumption. The proposed approach is implemented in Verilog HDL on Xilinx Virtex-7 FPGA XC7A35T-1FGG484C. The proposed method demonstrates remarkable accuracy enhancements in pattern recognition tasks, promising advancements in real-world applications.