Transition metal dichalcogenide FET-based dynamic random-access memory

Transition metal dichalcogenide field-effect transistors (TMDFETs) as a replacement for conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted the attention of researchers in recent years. The efficiency of these devices should be investigated in different aspects in digital systems. One of the important components of such systems is dynamic random-access memory (DRAM), which is used in most computers and many electronic systems as the main memory due to its small area and simple structure, compared to static memory (SRAM) cells. In this paper, a regular DRAM cell is designed based on TMDFET devices and its performance is compared with a similar cell in conventional MOSFET technology from various aspects, including DRAM-specific timing characteristics considering changes in design and environmental parameter variations using Monte Carlo simulations. The simulations have been carried out in HSPICE with 16 nm technology under fair conditions for different technologies, at room temperature with a 0.7-V power supply. The results show that the TMD-DRAM has 3.55x, 3.08x, and 2.23x faster bitline recovery, merge time, and sense time than Si-MOS-DRAM, respectively. The Si-MOS-DRAM, on the other hand, has 1.65x faster write time compared to TMD-DRAM. However, TMD-DRAM consumes overall higher power than Si-MOS-DRAM, and shows higher average read power variability with the sigma/mu = 0.476. The TMD-DRAM also shows higher variability in the studied timing characteristics than Si-MOS-DRAM except merge and sense times. A regular DRAM cell is designed based on Transition metal dichalcogenide FETs (TMDFET) devices. Monte Carlo simulations are performed to study different performance metrics such as bitline recovery time, merge time, sense time and power consumption. Simulations have been carried out in HSPICE with 16 nm technology. image