COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores

被引：0

作者：

Portero, Antoni ^{[1
]}

Falquez, Carlos ^{[1
]}

Ho, Nam ^{[1
]}

Petrakis, Polydoros ^{[2
]}

Nassyr, Stepan ^{[1
]}

Marazakis, Manolis ^{[2
]}

Dolbeau, Romain ^{[3
]}

Cifuentes, Jorge Alejandro Nocua ^{[4
]}

Alvarez, Luis Bertran ^{[4
]}

Pleiter, Dirk ^{[5
]}

Suarez, Estela ^{[1
]}

机构：

[1] Forschungszentrum Julich, Julich Supercomp Ctr, Novel Syst Architectures Design, Julich, Germany

[2] Fdn Res & Technol Hellas FORTH, Inst Comp Sci, Iraklion, Greece

[3] SiPearl, Rennes, France

[4] ATOS, Les Clayes Sous Bois, France

[5] Royal Inst Technol, KTH, Stockholm, Sweden

来源：

ARCHITECTURE OF COMPUTING SYSTEMS, ARCS 2023 | 2023年 / 13949卷

关键词：

Co-design; HPC; Network on Chip; gem5;

D O I：

10.1007/978-3-031-42785-5_8

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper explores the memory subsystem design through gem5 simulations of a non-uniform memory access (NUMA) architecture with ARM cores equipped with vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes provide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system.

引用

页码：105 / 119

页数：15

共 26 条

[1] Worst-Case Memory Traffic Analysis for Many-Cores using a Limited Migrative Model
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[2] A DECENTRALIZED APPROACH FOR MULTI-SUBSYSTEM CO-DESIGN OPTIMIZATION USING DIRECT COLLOCATION METHOD
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[3] Performance Analysis Techniques for the Exascale Co-Design Process
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Isaacs, Katherine E.
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Levine, Joshua
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[6] Adaptive Quantization as a Device-Algorithm Co-Design Approach to Improve the Performance of In-Memory Unsupervised Learning With SNNs
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Gupta, A
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[9] Impact of Small Antenna on Linear Power Amplifier Performance in a Co-design Approach
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Giry, Alexandre
Bories, Serge
Nicolas, Dominique
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[10] Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator
Rios-Navarro, A.
Tapiador-Morales, R.
Jimenez-Fernandez, A.
Amaya, C.
Dominguez-Morales, M.
Delbruck, T.
Linares-Barranco, A.
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