A Method for Simulating Mixed-Signal ATE Tests

被引：1

作者：

Sunter, Stephen ^{[1
]}

Zivkovic, Vladimir ^{[2
]}

Praselski, Bartlomiej ^{[1
]}

机构：

[1] Siemens Digital Ind Software, Ottawa, ON, Canada

[2] Infineon, Copenhagen, Denmark

来源：

2024 IEEE 42ND VLSI TEST SYMPOSIUM, VTS 2024 | 2024年

关键词：

analog test generation; IEEE P1687.2; IJTAG; DfT;

D O I：

10.1109/VTS60656.2024.10538577

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

It has never been practical to simulate production tests of mixed-signal ICs, except for the smallest ones. As a result, tests are written in the language of the intended automatic test equipment (ATE) and debugged on the ATE with (possibly defective) 'first silicon' devices - this typically requires months of effort. This paper shows why and how the Procedural Description Language (PDL) defined by IEEE P1687.2 can be used for writing tests that can be simulated before automatically and reliably translating them into ATE code. Examples are provided of automated translation to simulation testbenches that are compatible with manufacturing test limitations, as well as an example translation to (previously) digital-only IEEE 1450 STIL.

引用

页数：7

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