共 50 条
- [41] Evaluating the Practicability of Error-Detection Circuit Exposed to Single-Event Upsets in 65 nm CMOS Technology 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1115 - 1117
- [42] Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology Science China Information Sciences, 2016, 59
- [45] Single Event Effects Characterization Induced by Heavy Ions in 65-nm PLL 2022 22ND EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS, RADECS, 2022, : 112 - 114
- [47] Effectiveness of the layout approach in mitigating single event transients in 65-nm bulk CMOS process IEICE ELECTRONICS EXPRESS, 2018, 15 (13):
- [50] Characterization of single-event multiple cell upsets in a custom SRAM in a 65 nm triple-well CMOS technology Science China Technological Sciences, 2015, 58 : 1726 - 1730