A simple passive floating memristor emulator circuit

In this research article, we propose a passive two -terminal floating memristor emulator circuit (MEC). The proposed MEC consists of two NMOS transistors, one PMOS transistor and one capacitor. The MEC has a simple circuit topology structure and is more advantageous for integration, which has a chip area of only 218.04 mu m 2 . The circuit can operate without additional bias and performs well in the high frequency environment at 50 MHz. Some of the memristor's characteristics, such as pinched hysteresis loop and non -volatility, are verified using the Cadence Virtuoso environment with 0.18 mu m SMIC technology. The MEC has also been successfully proven to be effective and reliable through the temperature variation, process corner variation and Monte Carlo analysis. In addition, we built a circuit for experimental testing by using the CD4007s to verify the theoretical and simulated results. Finally, the proposed memristor emulator circuit is applied to logic circuits.