A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs

被引：1

作者：

Zhang, Zhaoyang ^{[1
]}

Liu, Zhichao ^{[1
]}

Liu, Feiran ^{[1
]}

Gao, Yinhai ^{[1
]}

Ma, Yuchen ^{[1
]}

Zhang, Yutong ^{[1
]}

Guo, An ^{[1
]}

Xiong, Tianzhu ^{[1
]}

Chen, Jinwu ^{[1
]}

Chen, Xi ^{[1
]}

Wang, Bo ^{[1
]}

Tang, Yuchen ^{[1
]}

Pu, Xingyu ^{[1
]}

Wang, Xing ^{[1
]}

Yang, Jun ^{[1
]}

Si, Xin ^{[1
]}

机构：

[1] Southeast Univ, Nanjing, Peoples R China

来源：

2024 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, CICC | 2024年

基金：

中国国家自然科学基金; 国家重点研发计划;

关键词：

D O I：

10.1109/CICC60959.2024.10529053

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页数：2

共 7 条

[1] A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs
Zhang, Zhaoyang
Zhang, Yanqi
Liu, Feiran
Liu, Zhichao
Gao, Yinhai
Ma, Yuchen
Zhang, Yutong
Guo, An
Xiong, Tianzhu
Chen, Jinwu
Chen, Xi
Wang, Bo
Tang, Yuchen
Yang, Jun
Si, Xin
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2025, 60 (03) : 949 - 962
[2] A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations
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Qiao, Xin
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[3] A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro
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[4] A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation
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[5] SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads
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[6] 15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips
Si, Xin
Tu, Yung-Ning
Huang, Wei-Hsing
Su, Jian-Wei
Lu, Pei-Jung
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2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), 2020, : 246 - +
[7] A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity
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