15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

被引：0

作者：

Si, Xin ^{[1
]}

Tu, Yung-Ning ^{[1
]}

Huang, Wei-Hsing ^{[1
]}

Su, Jian-Wei ^{[1
]}

Lu, Pei-Jung ^{[1
]}

Wang, Jing-Hong ^{[1
]}

Liu, Ta-Wei ^{[1
]}

Wu, Ssu-Yen ^{[1
]}

Liu, Ruhui ^{[1
]}

Chou, Yen-Chi ^{[1
]}

Zhang, Zhixiao ^{[1
]}

Sie, Syuan-Hao ^{[1
]}

Wei, Wei-Chen ^{[1
]}

Lo, Yun-Chen ^{[1
]}

Wen, Tai-Hsing ^{[1
]}

Hsu, Tzu-Hsiang ^{[1
]}

Chen, Yen-Kai ^{[1
]}

Shih, William ^{[1
]}

Lo, Chung-Chuan ^{[1
]}

Liu, Ren-Shuo ^{[1
]}

Hsieh, Chih-Cheng ^{[1
]}

Tang, Kea-Tiong ^{[1
]}

Lien, Nan-Chun ^{[3
]}

Shih, Wei-Chiang ^{[3
]}

He, Yajuan ^{[2
]}

Li, Qiang ^{[2
]}

Chang, Meng-Fan ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Hsinchu, Taiwan

[2] Univ Elect Sci & Technol China, Chengdu, Peoples R China

[3] M31 Technol, Hsinchu, Taiwan

来源：

2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC) | 2020年

关键词：

D O I：

10.1109/isscc19947.2020.9062995

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：246 / +

页数：3

共 24 条

[1] A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips
Si, Xin
Tu, Yung-Ning
Huang, Wei-Hsing
Su, Jian-Wei
Lu, Pei-Jung
Wang, Jing-Hong
Liu, Ta-Wei
Wu, Ssu-Yen
Liu, Ruhui
Chou, Yen-Chi
Chung, Yen-Lin
Shih, William
Lo, Chung-Chuan
Liu, Ren-Shuo
Hsieh, Chih-Cheng
Tang, Kea-Tiong
Lien, Nan-Chun
Shih, Wei-Chiang
He, Yajuan
Li, Qiang
Chang, Meng-Fan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56 (09) : 2817 - 2831
[2] A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips
Su, Jian-Wei
Chou, Yen-Chi
Liu, Ruhui
Liu, Ta-Wei
Lu, Pei-Jung
Wu, Ping-Chun
Chung, Yen-Lin
Hung, Li-Yang
Ren, Jin-Sheng
Pan, Tianlong
Li, Sih-Han
Chang, Shih-Chieh
Sheu, Shyh-Shyuan
Lo, Wei-Chung
Wu, Chih-, I
Si, Xin
Lo, Chung-Chuan
Liu, Ren-Shuo
Hsieh, Chih-Cheng
Tang, Kea-Tiong
Chang, Meng-Fan
2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2021, 64 : 250 - +
[3] 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips
Su, Jian-Wei
Si, Xin
Chou, Yen-Chi
Chang, Ting-Wei
Huang, Wei-Hsing
Tu, Yung-Ning
Liu, Ruhui
Lu, Pei-Jung
Liu, Ta-Wei
Wang, Jing-Hong
Zhang, Zhixiao
Jiang, Hongwu
Huang, Shanshi
Lo, Chung-Chuan
Liu, Ren-Shuo
Hsieh, Chih-Cheng
Tang, Kea-Tiong
Sheu, Shyh-Shyuan
Li, Sih-Han
Lee, Heng-Yuan
Chang, Shih-Chieh
Yu, Shimeng
Chang, Meng-Fan
2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), 2020, : 240 - +
[4] A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro
Pan, Nanbing
Cui, Xiaoxin
Qiao, Xin
Xiao, Kanglin
Guo, Qingyu
Wang, Yuan
2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 2561 - 2565
[5] An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips
Wu, Ping-Chun
Su, Jian-Wei
Chung, Yen-Lin
Hong, Li-Yang
Ren, Jin-Sheng
Chang, Fu-Chun
Wu, Yuan
Chen, Ho-Yu
Lin, Chen-Hsun
Hsiao, Hsu-Ming
Li, Sih-Han
Sheu, Shyh-Shyuan
Chang, Shih-Chieh
Lo, Wei-Chung
Wu, Chih-, I
Lo, Chung-Chuan
Liu, Ren-Shuo
Hsieh, Chih-Cheng
Tang, Kea-Tiong
Chang, Meng-Fan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59 (07) : 2297 - 2309
[6] A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications
Xiao, Kanglin
Cui, Xiaoxin
Qiao, Xin
Wang, Xin 'an
Wang, Yuan
MICROELECTRONICS JOURNAL, 2022, 126
[7] Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips
Su, Jian-Wei
Si, Xin
Chou, Yen-Chi
Chang, Ting-Wei
Huang, Wei-Hsing
Tu, Yung-Ning
Liu, Ruhui
Lu, Pei-Jung
Liu, Ta-Wei
Wang, Jing-Hong
Chung, Yen-Lin
Ren, Jin-Sheng
Chang, Fu-Chun
Wu, Yuan
Jiang, Hongwu
Huang, Shanshi
Li, Sih-Han
Sheu, Shyh-Shyuan
Wu, Chih-, I
Lo, Chung-Chuan
Liu, Ren-Shuo
Hsieh, Chih-Cheng
Tang, Kea-Tiong
Yu, Shimeng
Chang, Meng-Fan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (02) : 609 - 624
[8] A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation
Xiao, Kanglin
Cui, Xiaoxin
Qiao, Xin
Song, Jiahao
Luo, Haoyang
Wang, Xin'an
Wang, Yuan
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (06) : 1816 - 1820
[9] A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations
Xiao, Kanglin
Qiao, Xin
Cui, Xiaoxin
Song, Jiahao
Luo, Haoyang
Wang, Xin'an
Wang, Yuan
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71 (07) : 3263 - 3267
[10] A 8-h-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips
Su, Jian-Wei
Chou, Yen-Chi
Liu, Ruhui
Liu, Ta-Wei
Lu, Pei-Jung
Wu, Ping-Chun
Chung, Yen-Lin
Hong, Li-Yang
Ren, Jin-Sheng
Pan, Tianlong
Jhang, Chuan-Jia
Huang, Wei-Hsing
Chien, Chih-Han
Mei, Peng-, I
Li, Sih-Han
Sheu, Shyh-Shyuan
Chang, Shih-Chieh
Lo, Wei-Chung
Wu, Chih-, I
Si, Xin
Lo, Chung-Chuan
Liu, Ren-Shuo
Hsieh, Chih-Cheng
Tang, Kea-Tiong
Chang, Meng-Fan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2023, 58 (03) : 877 - 892

← 1 2 3 →