共 50 条
- [31] Reduced latency IEEE floating-point standard adder architectures Proceedings - Symposium on Computer Arithmetic, 1999, : 35 - 42
- [34] HARDWARE IMPLEMENTATION OF A FAST FLOATING-POINT ADDER FOR EMBEDDED SYSTEMS ELECTRONICS WORLD, 2014, 120 (1938): : 16 - 22
- [35] An Error Analysis Model for Floating-Point DFT Algorithms 2018 IEEE 61ST INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2018, : 532 - 535
- [37] Optimized UD filtering algorithm for floating-point hardware execution 2014 17TH INTERNATIONAL CONFERENCE ON INFORMATION FUSION (FUSION), 2014,