TRACE-DRIVEN PIPELINE AND CACHE SIMULATION OF MULTITHREADED COMPUTERS

A technique for applying trace-driven simulation to cached multithreaded machines with dynamic thread scheduling is presented. A small amount of constraint information is added to each trace record, permitting the correct order of execution in the pipeline to be constructed. Strategies like context switching on a cache miss, in which the behaviour of the cache affects the instruction dispatch order, can be modelled with this technique. The design of a multithreaded pipeline and cache trace-driven simulation system is described. This system allows thread-scheduled multithreaded processors, which are not simulatable by conventional trace-driven techniques, to be efficiently and accurately simulated. Samples simulation results illustrate the flexibility of this simulation technique.