SRAM Cell Optimization for Ultra-Low Power Standby

This paper proposes a comprehensive SRAM cell optimization scheme that minimizes leakage power under ultra-low standby supply voltage (VDD). The theoretical limit of data retention voltage (DRV), the minimum VDD that preserves the states of a memory cell, was derived to be 50 mV for an industrial 90 nm technology. A DRV design model was developed on parameters including body bias, sizing, and channel length. A test chip was implemented and measured to attain DRV sensitivities to key design parameters. Based on this, a low-leakage SRAM cell design methodology is derived and the feasibility of a 270 mV standby VDD was demonstrated, including a safety margin of 100 mV. As a result, the SRAM leakage power was reduced by 97%.