1-MU-M HIGH-SPEED CMOS IC TECHNOLOGY OPTIMIZED FOR LIQUID-NITROGEN TEMPERATURE OPERATION

被引：0
|
作者：
LI, YX
ZHANG, M
机构：
来源：
CRYOGENICS | 1990年 / 30卷
关键词：
D O I：
暂无
中图分类号：
O414.1 [热力学];
学科分类号：
摘要：
引用
收藏
页码：551 / 555
页数：5
相关论文
共 50 条
  • [21] A high-speed LVDS driver design in 0.35-μm CMOS technology
    Wang, Zhongyan
    Guo, Ai
    Pu, Yan
    Lecture Notes in Electrical Engineering, 2015, 334 : 1003 - 1010
  • [22] BIPOLAR CMOS MERGED TECHNOLOGY FOR HIGH-SPEED M-BIT DRAM
    KOBAYASHI, Y
    OOHAYASHI, M
    ASAYAMA, K
    IKEDA, T
    HORI, R
    ITOH, K
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1987, 134 (03) : C127 - C127
  • [23] A 1 MU-M CMOS TECHNOLOGY WITH LOW-TEMPERATURE PROCESSING
    SHARMA, D
    GOODWINJOHANSSON, S
    WEN, DS
    KIM, CK
    OSBURN, CM
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1987, 134 (03) : C117 - C117
  • [24] Device integration of a 0.35 mu m CMOS on shallow SIMOX technology for high-speed and low-power applications.
    Adan, AO
    Naka, T
    Kaneko, S
    Urabe, D
    Higashi, K
    Kagisawa, A
    1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 116 - 117
  • [25] QUASI-STATIC RAM DESIGN FOR HIGH-PERFORMANCE OPERATION AT LIQUID-NITROGEN TEMPERATURE
    JAEGER, RC
    BLALOCK, TN
    CRYOGENICS, 1990, 30 (12) : 1030 - 1035
  • [26] A high performance 0.25 mu m logic technology optimized for 1.8V operation
    Bohr, M
    Ahmed, SS
    Ahmed, SU
    Bost, M
    Ghani, T
    Greason, J
    Hainsey, R
    Jan, C
    Packan, P
    Sivakumar, S
    Thompson, S
    Tsai, J
    Yang, S
    IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, : 847 - 850
  • [27] Wide-temperature high-speed operation of a nematic liquid crystal cell
    Choi, Tae-Hoon
    Kim, Jung-Wook
    Yoon, Tae-Hoon
    EMERGING LIQUID CRYSTAL TECHNOLOGIES XII, 2017, 10125
  • [28] A 10 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes
    Zhang, Mingke
    Hu, Qingsheng
    International Journal of Control and Automation, 2014, 7 (11): : 299 - 302
  • [29] A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes
    张明科
    胡庆生
    Journal of Semiconductors, 2013, 34 (12) : 119 - 125
  • [30] A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes
    张明科
    胡庆生
    Journal of Semiconductors, 2013, (12) : 119 - 125
12345