EXPERIMENTAL COMPARISON OF MEMORY MANAGEMENT POLICIES FOR NUMA MULTIPROCESSORS

被引:31
|
作者
LAROWE, RP [1 ]
ELLIS, CS [1 ]
机构
[1] DUKE UNIV,DEPT COMP SCI,DURHAM,NC 27706
来源
关键词
EXPERIMENTATION; MANAGEMENT; MEASUREMENT; PERFORMANCE;
D O I
10.1145/118544.118546
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Nonuniformity of memory access is an almost inevitable feature of the memory architecture in shared memory multiprocessor designs that can scale to large numbers of processors. One implication of NUMA architectures is that the placement and movement of code and data are crucial to performance. As memory architectures become more complex and the nonuniformity becomes less well hidden, system software must assume a larger role in providing memory management support for the programmer. This paper investigates the role of the operating system. We take an experimental approach to evaluating a wide-range of memory management policies. The target NUMA environment is BBN's GP-1000 multiprocessor. Extensive local modifications have been made to the memory management subsystem of BBN's nX operating system to support multiple policy implementations. Policy comparisons are based on the measured performance of real parallel applications. Our results show that there are memory management policies implemented in our system that can improve the performance of programs written using the simpler uniform memory access (UMA) programming model. While achieving the level of performance of a highly tuned NUMA program is still a difficult problem, some examples come close. There appears to be no single policy that can be considered the best over our set of test applications. Investigations into the contributions made by individual policy features toward overall behavior of the workload provide some insight into the design of a set of effective policies.
引用
收藏
页码:319 / 363
页数:45
相关论文
共 50 条
  • [31] Traffic Management: A Holistic Approach to Memory Placement on NUMA Systems
    Dashti, Mohammad
    Fedorova, Alexandra
    Funston, Justin
    Gaud, Fabien
    Lachaize, Renaud
    Lepers, Baptiste
    Quema, Vivien
    Roth, Mark
    ACM SIGPLAN NOTICES, 2013, 48 (04) : 381 - 393
  • [32] Page-mapping techniques for CC-NUMA multiprocessors
    Huang, J
    Jin, GH
    Li, ZY
    ICA(3)PP 97 - 1997 3RD INTERNATIONAL CONFERENCE ON ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, 1997, : 91 - 104
  • [33] Optimizing the Memory Management of a Virtual Machine Monitor on a NUMA System
    Luo, Qiuming
    Xiao, Feng
    Ming, Zhong
    Li, Hao
    Chen, Jianyong
    Zhang, Jianhua
    COMPUTER, 2016, 49 (06) : 66 - 74
  • [34] Implementation and evaluation of directory hints in CC-NUMA multiprocessors
    Hsiao, HC
    King, CT
    PARALLEL COMPUTING, 2002, 28 (01) : 107 - 132
  • [35] A Comparison of Programming Models for Multiprocessors with Explicitly Managed Memory Hierarchies
    Schneider, Scott
    Yeom, Jae-Seung
    Rose, Benjamin
    Linford, John C.
    Sandu, Adrian
    Nikolopoulos, Dimitrios S.
    ACM SIGPLAN NOTICES, 2009, 44 (04) : 131 - 140
  • [36] Parallel Data Distribution Management on Shared-memory Multiprocessors
    Marzolla, Moreno
    D'angelo, Gabriele
    ACM TRANSACTIONS ON MODELING AND COMPUTER SIMULATION, 2020, 30 (01):
  • [37] Performance evaluation for CC-NUMA multiprocessors using an OLTP workload
    Chung, YW
    Kim, H
    Park, JW
    Lee, K
    MICROPROCESSORS AND MICROSYSTEMS, 2001, 25 (04) : 221 - 229
  • [38] The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors
    Acacio, ME
    González, J
    García, JM
    Duato, J
    2002 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, 2002, : 155 - 164
  • [39] Processor scheduling with page placement for cluster-based NUMA multiprocessors
    Koita, T
    Katayama, T
    Saisho, K
    Fukuda, A
    INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-IV, PROCEEDINGS, 1998, : 851 - 858
  • [40] The thread-based protocol engines for CC-NUMA multiprocessors
    Hsiao, HC
    King, CT
    2000 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING, PROCEEDINGS, 2000, : 497 - 504