ON THE VLSI DESIGN OF A PIPELINE REED-SOLOMON DECODER USING SYSTOLIC ARRAYS

被引：64
|
作者：
SHAO, HM
REED, IS
机构：
[1] CALTECH,JET PROP LAB,PASADENA,CA 91109
[2] UNIV SO CALIF,DEPT ELECT ENGN,LOS ANGELES,CA 90089
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1988年 / 37卷 / 10期
关键词：
D O I：
10.1109/12.5988
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
CODES, SYMBOLIC
引用
收藏
页码：1273 / 1280
页数：8
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