OPTIMUM DESIGN OF FAULT-TOLERANT ARITHMETIC ARRAY PROCESSORS BY USING DATA CODING

被引:0
|
作者
PIURI, V [1 ]
机构
[1] POLITECN MILAN,DEPT ELECTR,I-20133 MILAN,ITALY
来源
MICROPROCESSING AND MICROPROGRAMMING | 1989年 / 27卷 / 1-5期
关键词
D O I
10.1016/0165-6074(89)90135-X
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:697 / 704
页数:8
相关论文
共 50 条
  • [1] FAULT-TOLERANT HEXAGONAL ARITHMETIC ARRAY PROCESSORS
    PIURI, V
    MICROPROCESSING AND MICROPROGRAMMING, 1988, 24 (1-5): : 629 - 636
  • [2] Dynamic Fault-tolerant Design for Array Processors Based on Immunology
    Wu Ze-jun
    Wang Xin-an
    Li Guo-liang
    2ND IEEE INTERNATIONAL CONFERENCE ON ADVANCED COMPUTER CONTROL (ICACC 2010), VOL. 5, 2010, : 16 - 20
  • [3] Optimal fault-tolerant design approach for VLSI array processors
    Zhang, CN
    Bachtiar, TM
    Chou, WK
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1997, 144 (01): : 15 - 21
  • [4] FAULT-TOLERANT ARRAY PROCESSORS USING SINGLE-TRACK SWITCHES
    KUNG, SY
    JEAN, SN
    CHANG, CW
    IEEE TRANSACTIONS ON COMPUTERS, 1989, 38 (04) : 501 - 514
  • [5] FAULT-TOLERANT DESIGN OF LOCAL ESS PROCESSORS
    TOY, WN
    PROCEEDINGS OF THE IEEE, 1978, 66 (10) : 1126 - 1145
  • [7] An integrated fault-tolerant design framework for VLIW processors
    Chen, YY
    Horng, SJ
    Lai, HC
    18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, : 555 - 562
  • [8] Towards Fault-tolerant Design of Quaternary Quantum Arithmetic
    Zhu, Yunchen
    Yang, Ruixuan
    Gu, Yuhang
    Gu, Fangtian
    Kong, Lingyi
    Li, He
    8TH INTERNATIONAL TEST CONFERENCE IN ASIA, ITC-ASIA 2024, 2024,
  • [9] A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors
    Chen, YY
    Upadhyaya, SJ
    Cheng, CH
    IEEE TRANSACTIONS ON COMPUTERS, 1997, 46 (12) : 1363 - 1371