BIT-SERIAL VLSI SORTER WITH HIGH-RELIABILITY SPECIFICATIONS

被引：0

作者：

ADAMIDES, ED ^{[1
]}

TSALIDES, PG ^{[1
]}

THANAILAKIS, A ^{[1
]}

机构：

[1] DEMOCRITUS UNIV THRACE,DEPT ELECT & COMP ENGN,ELECTR & INFORMAT SYST TECHNOL SECT,GR-67100 XANTHI,GREECE

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1994年 / 40卷 / 08期

关键词：

PARALLEL SORTING; FAULT-TOLERANT COMPUTING; VLSI ARCHITECTURES; MODEL-BASED DESIGN; CELLULAR LOGIC;

D O I：

10.1016/0165-6074(94)90099-X

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design, operation and fault-tolerance enhancements of a parallel VLSI sorting architecture for bit-serial input which operates as a single pipelined comparator module. The basis design is enriched with a novel multiple redundancy fault-tolerance scheme so that the sorter meets high reliability specifications. Fault management operates locally at the most basic level of functionality. Hierarchical reconfiguration is supported by the fact that only data (no control) signals flow throughout the system. Reconfiguration is in real-time and automatic. The proposed sorter is a completely modular system having three levels of modularity, all exhibiting high regularity throughout. The sorting time is completely overlapped with the i/o time making the overall sorting process very fast. The sorter can sort N numbers of any length k without any modification.

引用

页码：523 / 536

页数：14

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