VLSI IMPLEMENTATION OF DIGIT-SERIAL ARITHMETIC MODULES

被引：1

作者：

BISDOUNIS, L

METAFAS, DE

MARAS, AM

MAVRIDIS, C

机构：

[1] UNIV PATRAS,DEPT ELECT ENGN,VLSI DESIGN LAB,GR-26110 PATRAI,GREECE

[2] UNIV CRETE,DEPT ELECTR & COMP ENGN,GR-73100 KHANIA,GREECE

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1993年 / 39卷 / 2-5期

关键词：

D O I：

10.1016/0165-6074(93)90099-7

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article describes an implementation of arithmetic modules which is based on the transmission of arithmetic data serially one digit at a time. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach.

引用

页码：251 / 254

页数：4

共 50 条

[21] Digit-Serial Pipeline Sorter Architecture
Yun-Nan Chang
Journal of Signal Processing Systems, 2010, 61 : 241 - 249
[22] Energy Reduction of Ultra-Low Voltage VLSI Circuits by Digit-Serial Architectures
Khan, Muhammad Umar Karim
Kyung, Chong Min
2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 3012 - 3017
[23] A DIGIT-SERIAL COMPILER OPERATOR LIBRARY
HARTLEY, R
CORBETT, P
1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 641 - 646
[24] Digit-Serial Pipeline Sorter Architecture
Chang, Yun-Nan
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2010, 61 (02): : 241 - 249
[25] A NEW DIGIT-SERIAL DIVIDER ARCHITECTURE
BASHAGHA, AE
IBRAHIM, MK
INTERNATIONAL JOURNAL OF ELECTRONICS, 1993, 75 (01) : 133 - 140
[26] Digit-serial Online arithmetic for high-speed digital signal processing applications
Natter, WG
Nowrouzian, B
CONFERENCE RECORD OF THE THIRTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1 AND 2, 2001, : 171 - 176
[27] Multiple constant multiplication for digit-serial implementation of low power FIR filters
Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden
WSEAS Trans. Circuits Syst., 2006, 7 (1001-1008):
[28] A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme
Bai, Xu
Okada, Nobuaki
Kameyama, Michitaka
JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2013, 20 (1-2) : 1 - 18
[29] Low-power digit-serial multipliers
Chang, YN
Satyanarayana, JH
Parhi, KK
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 2164 - 2167
[30] Configurable digit-serial convolver of type F
Milentijevic, IZ
Stojcev, MK
Maksimovic, DM
MICROELECTRONICS JOURNAL, 1996, 27 (06) : 559 - 566

← 1 2 3 4 5 →