DESIGN OF A DEDICATED NEURAL-NETWORK ON SILICON - APPLICATION TO OPTICAL CHARACTER-RECOGNITION

This paper presents the design of a dedicated chip achieving the recognition phase of an Optical Character Recognition (OCR) neural network (840 neurons in 4 layers plus 800 LVQ neurons). The target architecture is based on a basic block called the neuron processor. It contains a set of synaptic coefficients stored in a local memory and is able to perform the potential computation and any classical activation function (threshold, sigmoidal function,...). Such a processor is customizable and it may implement different arithmetic formats. The essential difficulties of integrating neural networks on silicon are mainly synaptic weights storage, interconnection implementation and processing power. The huge number of neurons (1640 neurons) has been integrated in only 5 processors implemented in a single chip called the OCR-chip. Four neuron processors (a single processor computes several states of different neurons), interconnected in a ring, perform the 31248 synaptic calculations of layers 1 to 4. This is why connections between neurons folded on the same processor must be described in each processor. Using address generator based on modulus m counters allows us to encode these connections in a very small area. A fifth processor (called the LVQ-processor) is used to compute the states of the LVQ neurons. This work has been done within the ESPRIT project Galatea in cooperation with SGS-Thomson and Thomson CSF.