ESTIMATION OF MAXIMUM CURRENTS IN MOS IC LOGIC-CIRCUITS

被引：47

作者：

CHOWDHURY, S

BARKATULLAH, JS

机构：

[1] Department of Electrical and Computer Engineering, University of Iowa, Iowa City

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1990年 / 9卷 / 06期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/43.55194

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Current estimates are needed in integrated circuits (IC) for accurate timing analysis and for reliable design of power and ground buses. Maximum current estimates are of particular interest, especially with respect to the design of power and ground buses. This paper deals with estimating currents in nMOS/CMOS IC logic circuits at three levels of hierarchies: gate level, macro-level, and power/ground distribution level. Models are developed for estimating currents in nMOS/CMOS gates. These models are used to estimate currents in a macro in response to input excitations. Algorithms are developed to estimate the maximum current requirement for a macro and to identify the input excitation at which the maximum current occurs. The macro-currents are used to estimate the maximum currents in the segments of power (ground) distribution systems. Some of the algorithms provide tradeoff between runtime and quality of solutions. Experimental results are included. © 1990 IEEE

引用

页码：642 / 654

页数：13

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