DESIGN ASPECTS OF SYNCHRONOUS PWM RECTIFIER-INVERTER SYSTEMS UNDER UNBALANCED INPUT VOLTAGE CONDITIONS

Synchronous front-end PWM rectifiers are compatible with variable-frequency inverters because they generate a near sinusoidal input current with a controllable power factor and allow for the instantaneous reversal of power flow. Of the numerous publications in this area, however, none has dealt with the problems caused by input line voltage unbalance. As this paper shows, such problems include a significant distortion in the input current waveforms, considerable increase in the dc capacitor ripple current and voltage, and more importantly, the generation of subharmonic components in the inverter output voltages. The objective of this paper is to analyze the effects of input line voltage unbalance starting with the distortion in the input line currents and extending to the dc bus components and inverter output line voltages and currents. Analytical results are next used to obtain system design curves as a function of input voltage unbalance for all major system components. Finally, key predicted results are verified on a 2-kVA prototype unit.