共 50 条
- [23] Genetic algorithm approach to high-level synthesis of digital circuits Int J Syst Sci, 5 (517-522):
- [24] A Binding Algorithm in High-Level Synthesis for Path Delay Testability 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2013, : 546 - 551
- [25] An evolutionary algorithm for the testable allocation problem in high-level synthesis ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 471 - 474
- [26] TAO: Techniques for Algorithm-Level Obfuscation during High-Level Synthesis 2018 55TH ACM/ESDA/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2018,
- [28] Constraints on the design of a high-level model of cognition PROCEEDINGS OF THE NINETEENTH ANNUAL CONFERENCE OF THE COGNITIVE SCIENCE SOCIETY, 1997, : 358 - 363
- [30] Control and data flow graph extraction for high-level synthesis VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, 2004, : 187 - 192