The densification of the interconnection of application-specific integrated circuits (ASIC's) and memories is presented in light of applications. The technology currently used in the manufacture of our macro-multichip modules is based on the association of thick-film multilayers and thin-film multilayers on a silicon substrate. We demonstrate that the interconnection of ASIC's requires the utilization of thin-film multilayers. However, since ASIC's are interconnected in an extremely dense manner, the relative area occupied by the memories increases substantially and currently amounts to approximately 50% of the substrate area. The 3-D interconnection technology allows reducing the occupied area by a factor of 7 or 8, and thus obtains ultra-dense multichip modules. This innovative interconnection approach consists of interconnecting the bare chips not in the XY plane, but along the Z-axis. The interconnection process entails interconnecting the four lateral areas (sides) of the “cube” formed by stacking n chips (n = 8–10) on top of one another. To do so, the chips are individually interconnected on a thin film identical to a TAB film by means of gold wires prior to “cubing.” These chips are standard, off-the-shelf, and bump-free devices. After passing electrical testing and burn-in, they are (hen “glued” on top of one another with the TAB film. After these n “chip + film” assemblies have been cured (polymerized), a trim operation is carried out to cut the n-chips cube out of the TAB-film carrier cube. The trim line is approximately 100 µm from the edge of the chips. The cube containing the n chips thus provides four lateral areas (sides) in which appear the cross sections of the gold wires connecting each lead of each chip to the corresponding leads on the flexible films. These gold wire cross sections may be interconnected in two different ways according to the number of chip inputs/outputs (I/O's) or the conductor pitch: 1) interconnection by direct writing, achieved by using a micropen and conducting polymer ink, intended for conductors with a width around 75 µm; 2) interconnection by thin-film techniques, achieved by depositing under vacuum niCr + Au or Ni + Au on a photoresist (lift-off technique), intended for conductors with a small width of 10–50 µm. In addition to an unprecedented enhancement in densification, this new technique also substantially improves the high frequency behavior of IC's. Inductances are very low, for example, since the longest conductor will not exceed 4.8 mm in length; that is, the capacitances of the conductors compared to those of the chips silicon lateral areas are up to 100 times less than they would be with an on-polyimide thin-film interconnection. An application consisting of a cube of eight stacked 256-Kb static random-access memories (256-Kb SRAM's) is being developed. This technique is especially well suited for memories, but we are studying the possibilities of extending it to other chips of different sizes; for example; • very low-power consuming hybrid complementary metal-oxide semiconductor (HCMOS) chips (i.e., very low capacitive loss), intended for portable equipment; • microprocessors with on-chip cache memories, etc.; • ultra-dense multichip modules (MCM's) like those presented in this paper. The feasibility of this new technique has been demonstrated. It now has to be qualified and industrialized. © 1990 IEEE
