FACE-OFF - VHDL VS VERILOG HDL FOR ASIC DESIGN AND SIGN-OFF

被引：0

作者：

LEVIA, O ^{[1
]}

SANGUIINETTI, J ^{[1
]}

机构：

[1] SYNOPSYS,MT VIEW,CA

来源：

COMPUTER DESIGN | 1994年 / 33卷 / 13期

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：A14 / A17

页数：4

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