MIXED LEVEL TEST-GENERATION FOR HIGH FAULT COVERAGE

被引：1
|
作者：
HUBNER, U [1 ]
HINSEN, H [1 ]
HOFEBAUER, M [1 ]
VIERHAUS, HT [1 ]
机构：
[1] GESELLSCH MATH & DATENVERARBEITUNG,EIS,W-5205 ST AUGUSTIN 1,GERMANY
来源：
MICROPROCESSING AND MICROPROGRAMMING | 1991年 / 32卷 / 1-5期
关键词：
Integrated Circuit Testing--Automatic Testing - Logic Devices--Gates;
D O I：
10.1016/0165-6074(91)90438-Y
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Methods for test generation providing high fault coverage for non-trivial faults in CMOS circuits have been a subject of intense research for several years. By test generation from switch level netlists, a good fault coverage is possible also for circuits including structures like complex gates and transmission gates. However, a prohibitive amount of computer time is necessary for large designs. This paper describes an efficient combination of switch level and gate level test generation providing robust 2-pattern pairs via dynamic coupling of test generators.
引用
收藏
页码：791 / 796
页数：6
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