INTEGRATED COST AND PRODUCTIVITY LEARNING IN CMOS SEMICONDUCTOR MANUFACTURING

This paper describes a cost and productivity learning process that was carried out on a large-capacity CMOS manufacturing line at the IBM Burlington facility from 1991 to 1993. Major productivity gains were realized through process and tool improvements affecting yield, and through work-in-progress optimization and scrap reduction. Significant cost learning was also accomplished through tool cost management, capital depreciation and space cost reductions. and manpower optimization.