A CMOS IMPLEMENTATION OF THE ESA/390 MAINFRAME ARCHITECTURE

被引：1

作者：

ROETHE, N ^{[1
]}

WILLE, U ^{[1
]}

机构：

[1] IBM DEUTSCHLAND GMBH,ENTWICKLUNG & FORSCH,W-7030 BOBLINGEN,GERMANY

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1991年 / 32卷 / 1-5期

关键词：

D O I：

10.1016/0165-6074(91)90348-W

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The ESA/390 high-end CISC architecture has been implemented using a 1.0 um CMOS standard cell technology. The resulting 4 chip, 2.5 Mio. transistor microprocessor is used in IBM's 9221 line of midrange systems. This paper gives an overview of the technology used and a description of the implementation. The dataflow and pipelining scheme are described. Instructions of low complexity are executed RISC-like in a single cycle under full hardware-control, while comple instructions are interpreted by microcode.

引用

页码：209 / 214

页数：6

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