VLSI CHIPSET FOR 16X16 ATM SWITCH RUNNING AT 500-MBIT/S PER PORT

被引：2

作者：

YEUNG, MS

WONG, PC

机构：

[1] Advanced Network Systems Laboratory, Department of Information Engineering, Chinese University of Hong Kong, Shatin, NT

来源：

ELECTRONICS LETTERS | 1995年 / 31卷 / 20期

关键词：

ASYNCHRONOUS TRANSFER MODE; SWITCHING CIRCUITS; VLSI;

D O I：

10.1049/el:19951218

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ATM VLSI chipset based on pipeline banyan [1] running at 500 Mbit/s per port is discussed. With 1 mu m CMOS technology, the control plane chip runs at 80 MHz, and the data plane chip is limited only by gate delay.

引用

页码：1719 / 1720

页数：2

共 9 条

[1] Implementation of 16x16 ATM switch fabric with pipelined architecture
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[2] A CMOS 2.4-GBPS 16X16 ATM SWITCH CHIP SET
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