A single-clock-driven gate driver using p-type, low-temperature polycrystalline silicon thin-film transistors

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31''WVGA (800 x 480) LCD panel, and the fabricated circuits were verified via simulations and measurements.