A circuit technology for a self-refresh 16Mb DRAM with less than 0.5 mu A/MB data-retention current

A 16M self-refresh DRAM achieving less than 0.5 mu A per megabyte data retention current has been developed, Several techniques to achieve low retention current, including a relaxed junction biasing (RTB) scheme, a plate-floating leakage-monitoring (PFM) system, and a V-BB pub-down word-line driver (PDWD) are described, An extension of data-retention time by three-fold and the refresh timer period by 30-fold over previously reported self-refresh DRAM's has been achieved. This results in a reduction of the ac refresh-current to less than 0.4 mu A per megabyte. Furthermore, the addition of a gate-received V-BB detector (GRD) reduces de retention current to less than 0.1 mu A per megabyte, This allows a 20-megabyte RAM disk to retain data for 2.5 years when powered by a single button-shaped 190-mAh lithium battery.