A fast transient response low dropout regulator with current control methodology

A transient performance optimized CCL-LDO regulator is proposed. In the CCL-LDO, the control method of the charge pump phase-locked loop is adopted. A current control loop has the feedback signal and reference current to be compared, and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current. The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-1-V and is not restricted by the reference voltage. With a 1 mu F decoupling capacitor, the experimental results based on a 0.13 mu m CMOS process show that the output voltage is 1.0 V; when the workload changes from 100 mu A to 100 mA transiently, the stable dropout is 4.25 mV, the settling time is 8.2 mu s and the undershoot is 5.11 mV; when the workload changes from 100 mA to 100 mu A transiently, the stable dropout is 4.25 mV, the settling time is 23.3 mu s and the overshoot is 6.21 mV. The PSRR value is more than 95 dB. Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.