Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators

被引：0

作者：

A. Chorevas

D. Reisis

机构：

[1] University of Athens,Electronics Laboratory, Physics Department

来源：

Journal of VLSI signal processing systems for signal, image and video technology | 2003年 / 35卷

关键词：

systolic architectures; FIR filter; QAM; VLSI;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

This paper presents efficient techniques for mapping FIR filter computation circuits for PAM and QAM modulators onto systolic arrays. The exploitation of the inherent symmetry of these problem instances and the use of Look-Up Tables (L.U.T.) in conjunction with the use of systolic architectures, increases the performance while keeping the VLSI area minimal. Exploiting parallelism and pipelining enhances the throughput and results in linear expandability of the FIR filter with respect to the bit accuracy and to the stage count.

引用

页码：179 / 186

页数：7

共 9 条

[1] Efficient systolic array mapping of FIR filters used in PAM-QAM modulators
Chorevas, A
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JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2003, 35 (02): : 179 - 186
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