Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC

In this letter, a more energy-efficient capacitor switching algorithm is proposed for successive approximation register analog-to-digital converters. By adopting floating capacitors and switching from the smallest one to the largest one rather than from the largest one to the smallest one, the switching energy has been significantly reduced because the floating capacitors do not consume any power until they are switched. Besides, to add one bit, the dummy capacitor is reused which is realized by C–2C structure instead of the unit capacitor C. Compared to the conventional architecture, the proposed capacitor switching method achieves 99.6 % energy saving and 87.21 % capacitor area reduction, respectively.