A Generalized Power Reduction Technique for Truncated Multiplier via Latching the Data Inputs and Error Compensating Carry

This research paper introduces a generalized technique to minimize power dissipation in truncated multipliers. Like full width multipliers, truncated multipliers also exhibit a behaviour where if a portion of the inputs remains unchanged, the corresponding part of the multiplier output will also remain unchanged. However, the error compensation circuit in truncated multipliers can generate varying error compensation values in successive operations. To address this, a novel cluster based approach is proposed utilizing a latch and correlation circuit to accurately capture changes in both inputs and error compensation carries, thereby saving power. Importantly, this technique preserves the inherent error characteristics observed in earlier studies of truncated multipliers. Experimental results demonstrate that the proposed technique can reduce dynamic power consumption by up to 26% in FFT and FIR filters. These findings contribute to the field of power-efficient designs in digital multipliers and signal processing applications while maintaining desired error characteristics.