An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations

被引：0
|
作者：
Massimo Conti
Paolo Crippa
Simone Orcioni
Marcello Pesare
Claudio Turchetti
Loris Vendrame
Silvia Lucherini
机构：
[1] Universita Politecnica deele Marche,Dipartimento di Elettronica, Intelligenza Artificiale e Telecommunicazionis
[2] MPG Flash CAD STMicroelectronics,undefined
[3] CR&D STMicroelectronics,undefined
来源：
Analog Integrated Circuits and Signal Processing | 2003年 / 37卷
关键词：
parametric yield; device mismatch; optimization; statistical process variations; CAD tool;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
In this paper a novel CAD methodology for yield enhancement of VLSI CMOS circuits including random device variations is presented. The methodology is based on a preliminary characterization of the technological process by means of specific test chips for accurate mismatch modeling. To this purpose, a very accurate position-dependent parameter mismatch model has been formulated and extracted. Finally a CAD tool implementing this model has been developed. The tool is fully integrated in an environment of existing commercial tools and it has been experimented in the STMicroelectronics Flash Memory CAD Group.
引用
收藏
页码：85 / 102
页数：17
相关论文
共 50 条
  • [1] An integrated CAD methodology for yield enhancement of VLSI CMOS circuits including statistical device variations
    Conti, M
    Crippa, P
    Orcioni, S
    Pesare, M
    Turchetti, C
    Vendrame, L
    Lucherini, S
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2003, 37 (02) : 85 - 102
  • [2] Statistical design techniques for yield enhancement of low voltage CMOS VLSI
    Tarim, TB
    Kuntman, HH
    Ismail, M
    ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : A331 - A334
  • [3] A design reliability methodology for CMOS VLSI circuits
    Oshiro, L
    Radojcic, R
    1995 INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORT, 1996, : 34 - 39
  • [4] Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits
    Ghavami, Behnam
    Raji, Mohsen
    Pedram, Hossein
    Pedram, Massoud
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (05) : 887 - 900
  • [5] A new methodology for the statistical analysis of VLSI CMOS circuits and its application to flash memories
    Conti, M
    Crippa, P
    Orcioni, S
    Pesare, M
    Turchetti, C
    Vendrame, L
    Lucherini, S
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 89 - 92
  • [6] A statistical performance simulation methodology for VLSI circuits
    Orshansky, M
    Chen, JC
    Hu, CM
    1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 402 - 407
  • [7] MODELING OF LITHOGRAPHY RELATED YIELD LOSSES FOR CAD OF VLSI CIRCUITS
    MALY, W
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1985, 4 (03) : 166 - 177
  • [8] Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits
    Luo, Pei-Wen
    Chen, Jwu-E
    Wey, Chin-Long
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2011, E94A (01): : 352 - 361
  • [9] Statistical Estimation of Leakage Power Bounds in CMOS VLSI Circuits
    Bountas, Dimitrios
    Evmorfopoulos, Nestor
    Dimitriou, George
    Dadaliaris, Antonios
    Floros, George
    Stamoulis, Georgios
    25TH PAN-HELLENIC CONFERENCE ON INFORMATICS WITH INTERNATIONAL PARTICIPATION (PCI2021), 2021, : 312 - 317
  • [10] Robust design and yield enhancement of low-voltage CMOS analog integrated circuits
    Tarim, TB
    Ismail, M
    Kuntman, HH
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2001, 48 (04) : 475 - 486
12345