Integrating advanced reasoning into a SAT solver

被引:0
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作者
Min Ding
Pushan Tang
Dian Zhou
机构
[1] Fudan University,ASIC & System State Key Laboratory, Microelectronics Department
关键词
satisfiability (SAT); formal verification; electronics design automation;
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学科分类号
摘要
In this paper, we present a SAT solver based on the combination of DPLL (Davis Putnam Logemann and Loveland) algorithm and Failed Literal Detection (FLD), one of the advanced reasoning techniques. We propose a Dynamic Filtering method that consists of two restriction rules for FLD: internal and external filtering. The method reduces the number of tested literals in FLD and its computational time while maintaining the ability to find most of the failed literals in each decision level. Unlike the pre-defined criteria, literals are removed dynamically in our approach. In this way, our FLD can adapt itself to different real-life benchmarks. Many useless tests are therefore avoided and as a consequence it makes FLD fast. Some other static restrictions are also added to further improve the efficiency of FLD. Experiments show that our optimized FLD is much more efficient than other advanced reasoning techniques.
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页码:366 / 378
页数:12
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