Electrical degradation mechanisms of nanoscale charge trap flash memories due to trapped charge in the oxide layer

被引:0
|
作者
Kyoung Wook Koh
Dong Hun Kim
Ju Tae Ryu
Tae Whan Kim
Keon-Ho Yoo
机构
[1] Hanyang University,Department of Electronics and Computer Engineering
[2] Kyung Hee University,Department of Physics and Research Institute for Basic Sciences
来源
关键词
SONOS; Fixed charge; Threshold voltage shift; CTF degradation; RTN;
D O I
暂无
中图分类号
学科分类号
摘要
The deterioration of the electrical characteristics of charge trap flash (CTF) memories with a silicon-oxide-nitride-oxide-silicon (SONOS) structure due to the charge traps in the oxide layers attributed to the random trapping and detrapping processes was investigated. Simulation results for the CTF memories showed that the threshold voltage shift was decreased by the charge trapped in the oxide layers in the SONOS structure and that the charge trapped in the blocking oxide had more significant effects than that trapped in the tunneling oxide. The degradation effects of the charge trapped in the blocking oxide on the electrical characteristics of the CTF memories were clarified by examining the vertical electric field in the device.
引用
收藏
页码:533 / 536
页数:3
相关论文
共 50 条
  • [1] Electrical degradation mechanisms of nanoscale charge trap flash memories due to trapped charge in the oxide layer
    Koh, Kyoung Wook
    Kim, Dong Hun
    Ryu, Ju Tae
    Kim, Tae Whan
    Yoo, Keon-Ho
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2015, 67 (03) : 533 - 536
  • [2] Masking Trapped Charge in Flash Memories
    Wachter-Zeh, Antonia
    Yaakobi, Eitan
    2015 53RD ANNUAL ALLERTON CONFERENCE ON COMMUNICATION, CONTROL, AND COMPUTING (ALLERTON), 2015, : 696 - 703
  • [3] Recent Advances in Charge Trap Flash Memories
    Sandhya, C.
    Singh, P. K.
    Gupta, S.
    Rohra, H.
    Shivatheja, M.
    Ganguly, U.
    Hofmann, R.
    Mukhopadhyay, G.
    Mahapatra, S.
    Vasi, J.
    2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY, 2009, : 192 - +
  • [4] Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory
    Kim, Seunghyun
    Kwon, Dae Woong
    Lee, Sang-Ho
    Park, Sang-Ku
    Kim, Youngmin
    Kim, Hyungmin
    Kim, Young Goan
    Cho, Seongjae
    Park, Byung-Gook
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17 (02) : 167 - 173
  • [5] Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories
    Chiu, Yung-Yueh
    Shirota, Riichiro
    ELECTRONICS, 2021, 10 (20)
  • [6] Memory technology -nanoscale Poly-FG and charge trap flash non-volatile memories
    Krishnamohan, Tejas
    Technical Digest - International Electron Devices Meeting, IEDM, 2008,
  • [7] Evaluation of gadolinium oxide as a blocking layer of charge-trap flash memory cell
    Pu, Jing
    Kim, Sun-Jung
    Kim, Young-Sun
    Cho, Byung Jin
    ELECTROCHEMICAL AND SOLID STATE LETTERS, 2008, 11 (09) : H252 - H254
  • [8] Effects of nitride trap layer properties on location of charge centroid in charge-trap flash memory
    Kim, Seunghyun
    Kim, Do-Bin
    Yu, Eunseon
    Lee, Sang-Ho
    Cho, Seongjae
    Park, Byung-Gook
    2017 SILICON NANOELECTRONICS WORKSHOP (SNW), 2017, : 79 - 80
  • [9] Investigation of Charge Loss Mechanisms in Planar and Raised STI Charge Trapping Flash Memories
    Xia, Zhiliang
    Kim, Dae Sin
    Lee, Ju-Yul
    Lee, Keun-Ho
    Park, Young-Kwan
    Yoo, Moon-Hyun
    Chung, Chilhee
    SISPAD 2010 - 15TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2010, : 233 - 236
  • [10] Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer
    Goel, N.
    Gilmer, D. C.
    Park, H.
    Diaz, V.
    Sun, Y.
    Price, J.
    Park, C.
    Pianetta, P.
    Kirsch, P. D.
    Jammy, R.
    IEEE ELECTRON DEVICE LETTERS, 2009, 30 (03) : 216 - 218