A 10-bit 200-MHz CMOS video DAC for HDTV applications

被引:0
|
作者
Jiaoying Huang
Yigang He
Yichuang Sun
Hui Liu
Hui Yang
机构
[1] Hunan University,College of Electrical & Information Engineering
[2] University of Hertfordshire,School of Electronic, Communication and Electrical Engineering
来源
Analog Integrated Circuits and Signal Processing | 2007年 / 52卷
关键词
Digital-to-analog converters; Current steering; Switching sequence; Spurious-free dynamic range (SFDR);
D O I
暂无
中图分类号
学科分类号
摘要
This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm2. When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.
引用
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页码:133 / 138
页数:5
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