Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling

被引:0
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作者
Sissades Tongsima
Chantana Chantrapornchai
Edwin H.-M. Sha
Nelson L. Passos
机构
[1] University of Notre Dame,Dept. of Computer Science and Engineering
[2] Midwestern State University,Dept. of Computer Science
关键词
Schedule Length; Pipeline Architecture; Initial Schedule; Loop Schedule; Data Hazard;
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学科分类号
摘要
Computation intensive DSP applications usually require parallel/pipelined processors in order to meet specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficient loop scheduling algorithm that reduces data hazards for such DSP applications. This algorithm has been embedded in a tool, called SHARP, which schedules a pipelined data flow graph to multiple pipelined units while hiding the underlying data hazards and minimizing the execution time. This paper reports significant improvement for some well-known benchmarks showing the efficiency of the scheduling algorithm and the flexibility of the simulation tool.
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页码:111 / 123
页数:12
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