A 2.4 GHz integer-N frequency synthesizer for ZigBee applications

This paper presents a fully integrated Integer-N Phase Locked Loop (INPLL) for ZigBee applications. In this paper the effects of delay in the reset path of Phase and Frequency Detector (PFD) and current gain mismatch in the Charge Pump (CP) on the spectral purity of the Local Oscillator (LO) signal of INPLL is studied theoretically. Then a linearization technique is introduced for a conventional CP to minimize the current gain mismatch and also a modified PFD is presented to achieve a fully symmetrical structure in order to simplify physical verification. The proposed linearization technique of the CP leads to minimize the current gain mismatch from 8.5 to 2.5 µA and the linearity range enhanced 7 times more than conventional structure. Finally, an INPLL is implemented in 0.18 µm CMOS standard to use in ZigBee applications. Reference spurs of the LO signal of the designed INPLL are suppressed more than 8 dBc/Hz when the linearization technique is incorporating in the INPLL. The power consumption of the whole INPLL with a 1.8 V DC supply is 9.15 mW.