Power-oriented delay budgeting for combinational circuits

被引：0

作者：

Mi, Jialin ^{[1
]}

Chen, Chunhong ^{[1
]}

Kwan, H. K. ^{[1
]}

机构：

[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON N9B 3P4, Canada

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

基金：

加拿大自然科学与工程研究理事会;

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we propose an approach of providing the best power-delay tradeoff for combinational circuits. This is done by so-called power-oriented delay budgeting which is to combine the delay-budgeting technique with aggressive power optimization. We discuss the impacts that both discrete cell library and circuit topology may have on the potential power reduction. Experimental results show that up to 65% (an average of 35%) power savings can be achieved without any delay penalty.

引用

页码：3033 / +

页数：2

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