Subsp a ce estimation by hierarchical neural PCA: Analog/digital implementation constraints

被引：0

作者：

Paraschiv-Ionescu, A ^{[1
]}

Jutten, C ^{[1
]}

Bouvier, G ^{[1
]}

机构：

[1] INP Grenoble, LIS, F-38031 Grenoble, France

来源：

ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL III: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper addresses the issue of hardware implementation of hierarchical neural principal component analysis (PCA). We attempt to show by experimental studies the effect of finite accuracy computations on the algorithm's performance, for both analog and digital implementation.

引用

页码：742 / 745

页数：4

共 6 条

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