A novel CMOS front-end circuit with low power,Low noise and variable gain for 5-GHz WLAN applications

被引：0
|
作者：
Min, L [1 ]
Wang, HY [1 ]
Li, YM [1 ]
Chen, HY [1 ]
机构：
[1] Tsing Hua Univ, Inst Microelect, Beijing, Peoples R China
来源：
2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Incorporating the low-IF architecture, a 5-GHz WLAN receiver front-end chip is implemented in a 0.18 mum CMOS technology. The chip contains a single-in differential-out low noise amplifier with 1.5dB noise figure (NF), 25dB voltage gain and less than 13mW power consumption, a folded structure downconversion mixer with 9.9dB single side band noise figure (SSB NF), 13.7dB voltage gain and +2.7dBm IIP3, consuming 10mA current under a 2V supply voltage. The chip also has a 12dB gain adjustment through a VGA cell placed in parallel with LNA's input.
引用
收藏
页码：266 / 269
页数：4
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