A 1V 10b 125MSample/s A/D converter using cascade amp-sharing and capacitance coupling techniques

被引：0

作者：

Honda, Kazutaka

Furuta, Masanori

Kawahito, Shoji

机构：

[1] Shizuoka Univ, Grad Sch Elect Sci & Technol, Hamamatsu, Shizuoka 4328011, Japan

[2] Shizuoka Univ, Elect Res Inst, Hamamatsu, Shizuoka 4328011, Japan

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ISCAS.2006.1692764

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a low-power low-distortion pipeline ADC with 1.0V supply voltage. A cascade amp-shating architecture and capacitor coupling class-AB amplifier are proposed for low-power dissipation under high-speed sampling. The capacitance coupling S/H stage suppresses the distortion caused by the insufficient gate-source voltage of sampling switches due to a low supply voltage. According to H-SPICE simulation results, the 10b 125MSample/s ADC in 90nm digital CMOS process achieves SNDR of 56dB with a power dissipation of only 21mW.

引用

页码：1031 / 1034

页数：4