Parallel architecture dedicated to image component labelling in O(n log n): FPGA implementation

被引：6
|
作者：
Mozef, E [1 ]
Weber, S [1 ]
Jaber, J [1 ]
Prieur, G [1 ]
机构：
[1] UNIV NANCY 1,LAB INSTRUMENTAT ELECT NANCY,F-54506 VANDOEUVRE NANCY,FRANCE
来源：
VISION SYSTEMS: SENSORS, SENSOR SYSTEMS, AND COMPONENTS | 1996年 / 2784卷
关键词：
parallel architecture; labelling; linear array processors; content addressable memory; intermediate level vision; FPGA;
D O I：
10.1117/12.248522
中图分类号：
O43 [光学];
学科分类号：
070207 ; 0803 ;
摘要：
引用
收藏
页码：120 / 125
页数：6
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