Stub Series Terminal Logic-Based Low-Power Thermal-Aware Vedic Multiplier Design on 40-nm FPGA

In this paper, we have proposed SSTL-based low-power energy efficient design on Vedic multiplier. SSTL is an acronym for Stub Series Terminated Logic. The paper presents the proficiency of Antyayor Dasakepi Vedic technique for multiplication that strikes a disparity in the real procedure of multiplication by itself. It allows comparable production of biased products and eliminates unnecessary steps of multiplication. The projected algorithm is represented using Verilog language, a hardware description language. Also, we analyzed how this integrated design is affected when it is operated in different regions under different temperatures: 10, 25, 40, 55, 70 degrees C. It is observed that at different ambient temperatures from 10 to 70 degrees C, there is 37.95, 58.85, 36.03, 34.84, 33.51% reduction in leakage power for SSTL2_1 as compared to SSTL2_II, SSTL15_DCI, SSTL18_DCI, there is 8.37, 8.39, 8.47, 8.50, 7.47% reduction in MAT for SSTL15_DCI as compared to SSTL2_II, SSTL2_I, SSTL18_DCI, and there is 17.29, 3.84, 6.72, 5.124, 4.135% reduction in JT for SSTL18_DCI as compared to SSTL2_II, SSTL15_DCI, SSTL2_I.