An FPGA implementation of a Hopfield optimized block truncation coding

This paper presents an implementation for image compression using variable block truncation coding (BTC) on a Field Programmable Gate Array (FPGA). The compression technique is improved by employing a cost function obtained using Hopfield neural network (HNN), upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus better compression ratios are achieved. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced The Xilinx VirtexE BTC implementation has shown to provide a processing speed of about 1.113 x 10(6) of pixels per second with a compression ratio which varies between 1.25 and 2 bits per pixel, according to the image homogeneity.