An application of improved space vector strategy based in digital direct synthesizers for a high-performance inverter

被引:0
|
作者
Silva, Rodrigo [1 ]
Huerta-Ruelas, Jorge A. [1 ]
de Dios Ortiz-Alvarado, Juan [2 ]
Mendoza-Mondragon, Fortino [3 ]
Hernandez Zavala, Antonio [1 ]
机构
[1] Inst Politecn Nacl CICATA IPN, Cerro Blanco 141, Queretaro 76090, Mexico
[2] Inst Politecn Nacl, UPIIG, Av Mineral Valenciana 200 Fracc, Guanajuato, Mexico
[3] LICORE AC, Av Felipe Carrillo Puerto 1001 Int 2A Zona Ind, Queretaro 76120, Mexico
关键词
Direct Digital Synthesizers; Fuzzy Logic Control; Induction motor; Space-vector modulation;
D O I
10.1016/j.conengprac.2021.104764
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
When performing commutation at induction motors based in PWM, a change in the switching frequency can take several clock cycles to be reflected in the windings generating harmonics that could damage the motor or generate an erroneous modulation. Most of the high-performance inverters use the Space Vector PWM given its minor switching losses and its capability to reduce the harmonics in the output signals. Nonetheless, the SVPWM requires complex calculation in online operation, which is the major concern for real-time implementations. Even that there are problems related to the development of technology that does not use the sine waveform to drive an induction motor and considering the availability and capability of Direct Digital Synthesizers (DDS) technology, we developed a hardware-software system to propose a modulation strategy called Space Vector DDS. The SVDDS can synthesize any digital waveform besides the sine waveform, becoming a more versatile approach. This proposal is the first one to couple the DDS in the commutation of an induction motor. As summary, the main features of our SVDDS system are its capability to synthesize any discrete waveform, improvement of control response parameters (13% for a load test and 12% for a speed test, compared with SVPWM), a low value of the total harmonic distortion index (4.88%) and reduction of the mathematical processing (system response of 21.364 ns).
引用
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页数:11
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