A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design

被引：0

作者：

Izumi, Shintaro ^{[1
]}

Takeuchi, Takashi ^{[1
]}

Matsuda, Takashi ^{[1
]}

Lee, Hyeokjong ^{[1
]}

Konishi, Toshihiro ^{[1
]}

Tsuruda, Koh ^{[1
]}

Sakai, Yasuharu ^{[1
]}

Kawaguchi, Hiroshi ^{[1
]}

Ohta, Chikara ^{[1
]}

Yoshimoto, Masahiko ^{[1
]}

机构：

[1] Kobe Univ, Dept Comp Sci & Syst Engn, Kobe, Hyogo 6578501, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2010年 / E93C卷 / 03期

关键词：

cross-layer design; sensor networks; sensor node; MAC protocol; time synchronization; low power;

D O I：

10.1587/transele.E93.C.261

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system. through a vertical cooperative design among circuits. architecture, and communication protocols The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver. 18051 microcontroller. and dedicated MAC processor The test chip occupies 3 x 3 mm(2) in a 180-nm CMOS process. including 1 38 M transistors It dissipates 58 0 mu W under a network environment

引用

页码：261 / 269

页数：9

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