On the design of a parallel link using rigid-flex PCB technology

This article is a case stud's on the design, on manufacluring issues, and on performance of an interconnect unit built as a multilayer rigid-flex printed circuit hoard. The intended use, connecting eight existing FPGA-boards installed in four PCs, presented serious design restrictions and challenges. The width of the interconnects was limited to 14.6mm at a length of 400mm. Fine-trace PCB technolop andfine-pitch SAM devices had to he used. For cost reasons, and to maintain niechanicalflexihility, the numher of flexible layers was limited. A total of 86 parallel traces needed to he placed on two lavers, at only 210 mu m edge-to-edge distance, resulting in what appeared to he a worst-case scenario with respect to crosstalk. Thus, signal integrity is the main focus of this paper. Nevertheless, crosstalk- is at a tolerable level in the final design. Currently the interconnect units, called GrisLinks, are being tested and integrated into the system. In our test environment, clock rates of 250MHz were achieved, for a maximum bandwidth of 2GBytels per link.