Jitter tolerant continuous-time sigma-delta A-D converter employing in-loop low-pass filter

被引：1

作者：

Kobayashi, Daisuke ^{[1
]}

Takagi, Shigetaka ^{[1
]}

Fujii, Nobuo ^{[1
]}

机构：

[1] Tokyo Inst Technol, Tokyo 1528552, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2007年 / E90A卷 / 02期

关键词：

continuous-time sigma-delta modulator; A-D converter; over-sampling data converter; jitter tolerance;

D O I：

10.1093/ietfec/e90-a.2.351

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a jitter tolerant continuous-time sigma-delta A-D converter structure as well as its design method. This method transforms a conventionally designed sigma-delta A-D converter into a jitter tolerant one. Jitter tolerance is provided by the modified feedback signal paths and a consequently inserted digital LPF. This method is applicable independently of a system order and the other specifications.

引用

页码：351 / 357

页数：7

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